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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
HDTMOS E-FET.TM Power Field Effect Transistor
N-Channel Enhancement-Mode Silicon Gate
This advanced high-cell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature
MTP60N06HD
Motorola Preferred Device
TMOS POWER FET 60 AMPERES 60 VOLTS RDS(on) = 0.014 OHM
TM
D
G CASE 221A-06, Style 5 TO-220AB S
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous -- Continuous @ 100C -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance -- Junction to Case -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RJC RJA TL Value 60 60 20 30 60 42.3 180 150 1.0 - 55 to 175 540 1.0 62.5 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ C/W C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
E-FET, Designer's and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value. REV 2
(c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995
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MTP60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 30 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ = 125C) Forward Transconductance (VDS = 5.0 Vdc, ID = 30 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDD = 30 Vdc, ID = 60 Adc, VGS = 10 Vdc, RG = 9.1 ) td(on) tr td(off) tf QT (VDS = 48 Vdc, ID = 60 Adc, VGS = 10 Vdc) Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr (IS = 60 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) ta tb QRR LD -- -- LS -- 7.5 -- 3.5 4.5 -- -- nH -- -- -- -- 0.99 0.89 60 36 24 0.143 1.2 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 14 197 50 124 51 12 24 21 26 394 102 246 71 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss -- -- -- 1950 660 147 2800 924 300 pF (Cpk 3.0) (3) VGS(th) 2.0 -- (Cpk 3.0) (3) RDS(on) -- VDS(on) -- -- gFS 15 20 -- -- -- 1.0 0.9 mhos 0.011 0.014 Vdc 3.0 7.0 4.0 -- Vdc mV/C Ohm (Cpk 2.0) (3) V(BR)DSS 60 -- IDSS -- -- IGSS -- -- 100 -- -- 10 100 nAdc -- 71 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 15)
Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. (3) Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA
nH
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Motorola TMOS Power MOSFET Transistor Device Data
MTP60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
120 VGS = 10 V I D , DRAIN CURRENT (AMPS) 100 9V 80 60 40 20 0 5V TJ = 25C 6V 120 8V 7V I D , DRAIN CURRENT (AMPS) 100 80 60 40 20 0 2.0 100C 25C TJ = - 55C 2.8 3.6 4.4 5.2 6.0 6.8 7.6 VDS 10 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)
VGS, GATE-TO-SOURCE VOLTAGE (Volts)
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.020 VGS = 10 V 0.018 TJ = 100C 0.016 0.014 0.012 0.010 0.008 0.006 0 10 20 30 40 50 - 55C 25C
0.0132 TJ = 25C 0.0128 0.0124 0.0120 0.0116 0.0112 0.0108 0.0104 0.0100 0 10 20 30 40 15 V VGS = 10 V
60
70
80
90
100 110 120
50
60
70
80
90
100 110 120
ID, DRAIN CURRENT (Amps)
ID, DRAIN CURRENT (Amps)
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 - 50 VGS = 10 V ID = 30 A
1000 VGS = 0 V TJ = 125C I DSS, LEAKAGE (nA) 100 100C 25C 10
1 - 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
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MTP60N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
5000 Ciss 4000 C, CAPACITANCE (pF)
VDS = 0 V
VGS = 0 V TJ = 25C
3000 Crss 2000 Coss 1000 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 Ciss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTP60N06HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 VGS 8 Q1 6 4 2 Q3 0 0 8 16 24 32 40 VDS 48 QT, TOTAL GATE CHARGE (nC) ID = 60 A TJ = 25C Q2 30 20 10 0 56 40 50 60 1000 VDD = 30 V ID = 60 A VGS = 10 V TJ = 25C t, TIME (ns)
tr tf
100
td(off)
td(on) 10 1 10 RG, GATE RESISTANCE (Ohms) 100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short t rr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high
60 I S , SOURCE CURRENT (AMPS) 50 40 30 20 10 0 0.5 VGS = 0 V TJ = 25C
di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
0.6
0.7
0.8
0.9
1.0
VSD, SOURCE-TO-DRAIN VOLTAGE (Volts)
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
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MTP60N06HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
I D , DRAIN CURRENT (AMPS)
VGS = 20 V SINGLE PULSE TC = 25C 100 10 s
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)
1000
600 ID = 60 A 500 400 300 200 100 0
100 s 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 1.0 1 ms 10 ms dc 10 100
25
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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Motorola TMOS Power MOSFET Transistor Device Data
MTP60N06HD
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
1.0E+00
1.0E+01
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
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MTP60N06HD
PACKAGE DIMENSIONS
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04
-T- B
4
SEATING PLANE
F T S
C
Q
123
A U K
STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN
H Z L V G D N R J
CASE 221A-06 ISSUE Y
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Motorola TMOS Power MOSFET Transistor Device Data MTP60N06HD/D
*MTP60N06HD/D*

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